SH7261 Datasheet, PDF (165/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
3 to 0 BN[3:0]* 0000 R Bank Number
These bits indicate the bank number to which saving is
performed next. When an interrupt using register banks
is accepted, saving is performed to the register bank
indicated by these bits, and BN is incremented by 1.
After BN is decremented by 1 due to execution of a
RESBANK (restore from register bank) instruction,
restoration from the register bank is performed.
Note: * Bits BN[3:0] are initialized at a manual reset.
6.3.10 DMA Transfer Request Enable Register 0 (DREQER0)
DMA transfer request enable register 0 (DREQER0) is an 8-bit readable/writable register that
enables/disables the IIC3 DMA transfer requests, and enables/disables CPU interrupt requests.
DMA transfer request enable register 0 is initialized by a power-on reset or in deep standby mode.
Bit: 7
6
5
4
3
2
1
0
Reserved
IIC3 IIC3 IIC3 IIC3 IIC3 IIC3
2ch TX 2ch RX 1ch TX 1ch RX 0ch TX 0ch RX
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
7
Reserved
0
R/W DMA Transfer Request Enable Bits
6
Reserved
0
5
IIC3 2ch TX 0
4
IIC3 2ch RX 0
3
IIC3 1ch TX 0
2
IIC3 1ch RX 0
R/W These bits enable/disable DMA transfer requests, and
R/W ^{enable/disable CPU interrupt requests.}
R/W
0: DMA transfer request disabled, CPU interrupt
request enabled
R/W _{1: DMA transfer request enabled, CPU interrupt request}
R/W
disabled
1
IIC3 0ch TX 0
R/W
0
IIC3 0ch RX 0
R/W
Rev. 2.00 Sep. 07, 2007 Page 133 of 1312
REJ09B0320-0200