SH7261 Datasheet, PDF (231/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 8 Cache
Table 8.8 Cache Operations
Cache
Hit/
CPU Cycle miss
Instruction Instruction Hit
cache
fetch
Write-back mode/
write through mode

External Memory
Accession
U Bit (through internal bus)
 Not generated
Cache Contents
Not renewed
Miss 
 Cache renewal cycle is Renewed to new values by
generated.
cache renewal cycle
Operand Prefetch/ Hit
cache
read
Either mode is available x
Not generated
Not renewed
Miss Write-through mode
 Cache renewal cycle is Renewed to new values by
generated.
cache renewal cycle
Write-back mode
0
Cache renewal cycle is Renewed to new values by
generated
cache renewal cycle
1
Cache renewal cycle is Renewed to new values by
generated. Succeedingly cache renewal cycle
write-back cycle in write-
back buffer is generated
Write
Hit
Write-through mode
 Write cycle CPU issues is Renewed to new values by
generated.
write cycle the CPU issues
Write-back mode
x
Not generated
Renewed to new values by
write cycle the CPU issues
Miss Write-through mode
 Write cycle CPU issues is Not renewed*
generated.
Write-back mode
0
Cache renewal cycle is Renewed to new values by
generated.
cache renewal cycle.
Subsequently renewed
again to new values in
write cycle CPU issues.
1
Cache renewal cycle is Renewed to new values by
generated. Succeedingly cache renewal cycle.
write-back cycle in write- Subsequently renewed
back buffer is generated again to new values in
write cycle CPU issues.
[Legend]
x:
Don't care
Note: Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte
write access
* Neither LRU renewed. LRU is renewed in all other cases.
Rev. 2.00 Sep. 07, 2007 Page 199 of 1312
REJ09B0320-0200