SH7261 Datasheet, PDF (979/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Figure 21.4 is a schematic diagram of the stream-data input control block. The stream-data input
controller contains logic that controls the stream of input data and a register that is used to change
the control mode of the CD-ROM decoder.
The SSI mode used to transfer the stream data may affect the order (through the endian setting) or
lead to padding before the data is transferred. To handle the different arrangements of data
appropriately, the stream-data input control block includes a register for changing the operating
mode and generates signals to control the core of the CD-ROM decoder.
The data-pending registers for the input stream consists of two 16-bit registers. The data-pending
registers are controlled according to the mode set in the control register. For example, controlling
the order in which 16-bit data is supplied to the core of the CD-ROM decoder (sending the second
16-bytes first or vice versa). It is also possible to stop the supply of padding data to the core of the
CD-ROM decoder.
Input stream data
Register data
Register access controller
16 bits
16 bits
Select
Input stream controller
Figure 21.4 Schematic Diagram of the Stream-Data Input Control Block
Rev. 2.00 Sep. 07, 2007 Page 947 of 1312
REJ09B0320-0200