SH7261 Datasheet, PDF (1013/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Bit Bit Name
Initial
Value R/W Description
2
CBUF_TS
1
R/W CBUFCTL1 to CBUFCTL3 Setting Mode
0: Minutes, seconds, and frames values in BCD
1: Total number of sectors (in hexadecimal)
1
CBUF_Q
0
R/W Q-channel code buffering data specification in the case
of a CRC error in the Q-channel code
0: The values for the last sector for which the CRC
returned a correct result are buffered.
1: The erroneous data is buffered as is.
Since subcodes are not input with this LSI, always set
this bit to 1.
0

0
R/W Reserved
This bit is always read as 0.The write value should
always be 0.
21.3.42 Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1)
CBUFCTL1 indicates the minutes value in the header for the first sector to be buffered.
Bit: 7
6
5
4
3
2
1
0
BS_MIN[7:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 0
Bit Name
BS_MIN[7:0]
Initial
Value
All 0
R/W Description
R/W Setting of the minutes value in the header for the first
sector to be buffered
Rev. 2.00 Sep. 07, 2007 Page 981 of 1312
REJ09B0320-0200