SH7261 Datasheet, PDF (751/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.10 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear TE and RE bits
in SCSCR to 0
[1]
Set TFRST and RFRST bits
in SCFCR to 1 to clear
the FIFO buffer
After reading ER, DR,
and BRK flags in SCFSR,
write 0 to clear them
Set data transfer format
in SCSMR
[2]
Set CKE[1:0] bits
in SCSCR (leaving TE, RE, TIE,
[3]
and RIE bits cleared to 0)
Set value in SCBRR
[4]
Set RTRG[1:0] and TTRG[1:0] bits
in SCFCR, and clear TFRST
and RFRST bits to 0
PFC setting for external pins used _[5]
SCK, TxD, RxD
Set TE and RE bits in SCSCR to 1, [6]
and set TIE, RIE, and REIE bits
[1] Leave the TE and RE bits cleared
to 0 until the initialization almost
ends.
[2] Set the data transfer format in
SCSMR.
[3] Set the CKE1 and CKE0 bits.
[4] Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used.
[5] Sets PFC for external pins used.
Set as RxD input at reciving and
TxD at transmission.
[6] Set the TE or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits to enable the TxD,
RxD, and SCK pins to be used.
When transmitting, the TxD pin
will go to the mark state.
When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCK pin at this
point.
End of initialization
Figure 16.10 Sample Flowchart for SCIF Initialization
Rev. 2.00 Sep. 07, 2007 Page 719 of 1312
REJ09B0320-0200