SH7261 Datasheet, PDF (831/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
18.4.4 Transmit Operation
Transmission can be controlled either by DMA or interrupt.
DMA control is preferred to reduce the processor load. In DMA control mode the processor will
only receive interrupts if there is an underflow or overflow of data or the DMAC has finished its
transfer.
The alternative method is using the interrupts that the SSI module generates to supply data as
required. This mode has a higher interrupt load as the module is only double buffered and will
require data to be written at least every system word period.
When disabling the module, the SSI clock* must remain present until the SSI module is in idle
state, indicated by the IIRQ bit.
Figure 18.20 shows the transmit operation in DMA control mode, and figure 18.21 shows the
transmit operation in interrupt control mode.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Input clock from the AUDIO_CLK pin, or AUDIO_X1 and AUDIO_X2 pins when
SCKD = 1.
Rev. 2.00 Sep. 07, 2007 Page 799 of 1312
REJ09B0320-0200