SH7261 Datasheet, PDF (912/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
20.1.2 Communications Protocol
Figure 20.1 shows an IEBus transfer signal format.
Communications data is transferred as a series of signals referred to as a communications frame.
The number of data which can be transmitted in a single communications frame and the transfer
speed differ according to the communications mode.
(When IEBφ = 6, 12, 18, 24, 30, or 36 MHz)
Field name
Number
of bits
Transfer
time
Header
11
Master
address field
12 1
Start ^Broad- Master
bit ^cast address
P
bit
Slave address
field
12 1 1
Slave _{P A}
address
Control field Message
length field
4 11 8 11
Control
bits
P
A
Message
length
P
A
bits
8
Data
bits
Data field
11
PA
8
Data
bits
11
PA
Mode 0
Approximately 7330 µs
Approximately 1590 × N µs
Mode 1
Approximately 2090 µs
Approximately 410 × N µs
Mode 2
Approximately 1590 µs
Approximately 300 × N µs
P: Parity bit (1 bit)
A: Acknowledge bit (1 bit)
When A = 0: ACK
When A = 1: NAK
N: Number of bytes
Note: The value of acknowledge bit is ignored in broadcast communications.
Figure 20.1 Transfer Signal Format
(1) Header
A header is comprised of a start bit and a broadcast bit.
(a) Start Bit
The start bit is a signal to inform other units of the start of data transfer. A unit attempting to start
data transfer outputs a low-level signal (the start bit) for a specified period and then outputs the
broadcast bit.
If another unit is already outputting a start bit when a unit attempts to output a start bit, the unit
waits for completion of the start bit from the other unit without outputting its own start bit, and
then outputs the broadcast bit synchronized with the completion timing.
Other units enter the receive state after detecting the start bit.
Rev. 2.00 Sep. 07, 2007 Page 880 of 1312
REJ09B0320-0200