SH7261 Datasheet, PDF (669/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 14 Watchdog Timer (WDT)
14.5.4 Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset
occurs during DMAC burst transfer, manual reset exception handling will be pended until the
CPU acquires the bus mastership.
However, if the duration from generation of the manual reset to the bus cycle end is equal to or
longer than the duration of the internal manual reset activated, the occurrence of the internal
manual reset source is ignored instead of being pended, and the manual reset exception handling is
not executed.
Rev. 2.00 Sep. 07, 2007 Page 637 of 1312
REJ09B0320-0200