SH7261 Datasheet, PDF (649/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
13.5.4 Timing of Counter Clear by Compare Match
TCNT is cleared when compare match A or B occurs, depending on the settings of bits CCLR1
and CCLR0 in TCR. Figure 13.8 shows the timing of this operation.
Pφ
Compare match
signal
TCNT
N
H'00
Figure 13.8 Timing of Counter Clear by Compare Match
13.5.5 Timing of TCNT External Reset
TCNT is cleared at the rising edge or high level of an external reset input, depending on the
settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states.
Figures 13.9 and 13.10 show the timing of this operation.
Pφ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 13.9 Timing of Clearance by External Reset (Rising Edge)
Pφ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 13.10 Timing of Clearance by External Reset (High Level)
Rev. 2.00 Sep. 07, 2007 Page 617 of 1312
REJ09B0320-0200