SH7261 Datasheet, PDF (9/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Contents
Section 1 Overview................................................................................................1
1.1 SH7261 Group Features......................................................................................................... 1
1.2 Product Lineup..................................................................................................................... 10
1.3 Block Diagram ..................................................................................................................... 11
1.4 Pin Assignments................................................................................................................... 12
1.5 Pin Functions ....................................................................................................................... 15
Section 2 CPU......................................................................................................23
2.1 Register Configuration......................................................................................................... 23
2.1.1 General Registers.................................................................................................... 23
2.1.2 Control Registers .................................................................................................... 24
2.1.3 System Registers..................................................................................................... 26
2.1.4 Register Banks ........................................................................................................ 27
2.1.5 Initial Values of Registers....................................................................................... 27
2.2 Data Formats........................................................................................................................ 28
2.2.1 Data Format in Registers ........................................................................................ 28
2.2.2 Data Formats in Memory ........................................................................................ 28
2.2.3 Immediate Data Format .......................................................................................... 29
2.3 Instruction Features.............................................................................................................. 30
2.3.1 RISC-Type Instruction Set...................................................................................... 30
2.3.2 Addressing Modes .................................................................................................. 34
2.3.3 Instruction Format................................................................................................... 38
2.4 Instruction Set ...................................................................................................................... 42
2.4.1 Instruction Set by Classification ............................................................................. 42
2.4.2 Data Transfer Instructions....................................................................................... 48
2.4.3 Arithmetic Operation Instructions .......................................................................... 52
2.4.4 Logic Operation Instructions .................................................................................. 55
2.4.5 Shift Instructions..................................................................................................... 56
2.4.6 Branch Instructions ................................................................................................. 57
2.4.7 System Control Instructions.................................................................................... 58
2.4.8 Floating Point Operation Instructions ..................................................................... 60
2.4.9 FPU-Related CPU Instructions ............................................................................... 62
2.4.10 Bit Manipulation Instructions ................................................................................. 63
2.5 Processing States.................................................................................................................. 64
Rev. 2.00 Sep. 07, 2007 Page ix of xxxii