SH7261 Datasheet, PDF (332/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
(2) Error Notification to the CPU
The CPU is notified of a bus error through the OR condition of the timeout bits (PTO/CTO/ETO)
and illegal address access bits (PER/CER/EER/OER/SHER) in the bus monitor status register 1
(SYCBESTS1) and bus monitor status register 2 (SYCBESTS2). The CPU is notified of a bus
error interrupt according to the setting of the bus error control register (SYCBESW).
When the bus monitor status register 1 (SYCBESTS1) and bus monitor status register 2
(SYCBESTS2) are cleared by the CPU, the bus error interrupt signal is also negated.
(3) Termination of Bus Access
When a bus error is detected, the bus access is terminated. For details, see section 10.2.4,
Combinations of Masters and Bus Errors.
For the detailed operations when each type of error is detected, see section 10.2.2, Illegal Address
Access Detection Function and section 10.2.3, Bus Timeout Detection Function.
10.2.2 Illegal Address Access Detection Function
The illegal address access detection function detects attempted accesses to illegal addresses.
(1) Conditions of Illegal Address Access Error Generation
Illegal address access errors occur when the following illegal addresses are accessed.
• External spaces for which the operation enable bit (EXENB) in the control register of the BSC
is not set to "operation enabled"
• Other address areas that are not mapped to any slave bus
• Address areas that are mapped to the slave buses but do not correspond to slave devices
Tables 10.3 to 10.5 show the address areas to which slave devices are not mapped within the
spaces for peripheral buses (1), (2), and (3).
Table 10.3 Address Areas without Slave Devices in the Space for Peripheral Bus (1)
FF401000 to FF41FFFF
FF423000 to FF45FFFF
FF464000 to FF5FFFFF
Rev. 2.00 Sep. 07, 2007 Page 300 of 1312
REJ09B0320-0200