SH7261 Datasheet, PDF (132/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Exception Handling
Exception Sources
Vector
Numbers Vector Table Address Offset
(Reserved by system)
19
H'0000004C to H'0000004F
:
:
31
H'0000007C to H'0000007F
Trap instruction (user vector)
32
H'00000080 to H'00000083
:
:
63
H'000000FC to H'000000FF
External interrupts (IRQ, PINT), on-chip
64
peripheral module interrupts^*
:
H'00000100 to H'00000103
:
255
H'000003FC to H'000003FF
Note: * The vector numbers and vector table address offsets for each external interrupt and on-
chip peripheral module interrupt are given in table 6.4 in section 6, Interrupt Controller
(INTC).
Table 5.4 Calculating Exception Handling Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, bus errors,
register bank errors, interrupts,
instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. Vector table address offset: See table 5.3.
2. Vector number: See table 5.3.
Rev. 2.00 Sep. 07, 2007 Page 100 of 1312
REJ09B0320-0200