SH7261 Datasheet, PDF (891/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

(4) CAN sleep mode
Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Halt Request
Sleep Mode
Sequence flow
Write MCR[1] = 1
GSR[4] = 1?
No
Yes
IRR[0] = 1
Write IRR[0] = 1
IRR[0] = 0
Sleep Request Write MCR[1] = 0 & MCR[5] = 1
IRR[0] = 1
Write IRR[0] = 1
IRR0 = 0
Sleep Mode
User monitor
: Hardware operation
: Manual operation
CAN Bus Activity
No
Yes
IRR[12] = 1
MCR[7] = 1?
No
Yes
MCR[5] = 0
Write IRR[12] = 1
IRR[12] = 0
No
GSR4 = 0?
Yes
Transmission/Reception Mode
Write IRR[12] = 1
IRR[12] = 0
Write MCR[5] = 0
CLK is
STOP
Only MCR, GSR,
IRR, IMR can be
accessed.
User monitor
Figure 19.7 Halt Mode/Sleep Mode
Rev. 2.00 Sep. 07, 2007 Page 859 of 1312
REJ09B0320-0200