SH7261 Datasheet, PDF (92/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.4.8 Floating Point Operation Instructions
Table 2.17 Floating Point Operation Instructions
Instruction
FABS
FRn
FABS
DRn
FADD
FRm, FRn
FADD
DRm, DRn
FCMP/EQ FRm, FRn
Instruction Code
Operation
1111nnnn01011101 |FRn|→FRn
1111nnn001011101 |DRn|→DRn
1111nnnnmmmm0000 FRn+FRm→FRn
1111nnn0mmm00000 DRn+DRm→DRn
1111nnnnmmmm0100 (FRn=FRm)? 1:0→T
FCMP/EQ DRm, DRn
1111nnn0mmm00100 (DRn=DRm)? 1:0→T
FCMP/GT FRm, FRn
1111nnnnmmmm0101 (FRn>FRm)? 1:0→T
FCMP/GT DRm, DRn
1111nnn0mmm00101 (DRn>DRm)? 1:0→T
FCNVDS
FCNVSD
FDIV
FDIV
FLDI0
FLDI1
FLDS
FLOAT
FLOAT
FMAC
FMOV
FMOV
FMOV.S
FMOV.D
FMOV.S
FMOV.D
DRm, FPUL
FPUL, DRn
FRm, FRn
DRm, DRn
FRn
FRn
FRm, FPUL
FPUL,FRn
FPUL,DRn
FR0,FRm,FRn
FRm, FRn
DRm, DRn
@(R0, Rm), FRn
@(R0, Rm), DRn
@Rm+, FRn
@Rm+, DRn
1111mmm010111101
1111nnn010101101
1111nnnnmmmm0011
1111nnn0mmm00011
1111nnnn10001101
1111nnnn10011101
1111mmmm00011101
1111nnnn00101101
1111nnn000101101
1111nnnnmmmm1110
1111nnnnmmmm1100
1111nnn0mmm01100
1111nnnnmmmm0110
1111nnn0mmmm0110
1111nnnnmmmm1001
1111nnn0mmmm1001
(float)DRm→FPUL
(double)FPUL→DRn
FRn/FRm→FRn
DRn/DRm→DRn
0×00000000→FRn
0×3F800000→FRn
FRm→FPUL
(float)FPUL→FRn
(double)FPUL→DRn
FR0×FRm+FRn→FRn
FRm→FRn
DRm→DRn
(R0+Rm) →FRn
(R0+Rm) →DRn
(Rm) →FRn, Rm+=4
(Rm) →DRn, Rm+=8
Compatibility
Execution
Cycles
T Bit
SH2E SH4
SH-2A/
SH2A-FPU
1

Yes Yes Yes
1

Yes Yes
1

Yes Yes Yes
6

Yes Yes
1
Operation Yes Yes Yes
result
2
Operation
result
Yes Yes
1
Operation Yes Yes Yes
result
2
Operation
result
Yes Yes
2

Yes Yes
2

Yes Yes
10

Yes Yes Yes
23

Yes Yes
1

Yes Yes Yes
1

Yes Yes Yes
1

Yes Yes Yes
1

Yes Yes Yes
2

Yes Yes
1

Yes Yes Yes
1

Yes Yes Yes
2

Yes Yes
1

Yes Yes Yes
2

Yes Yes
1

Yes Yes Yes
2

Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 60 of 1312
REJ09B0320-0200