SH7261 Datasheet, PDF (334/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
Table 10.5 Address Areas without Slave Devices in the Space for Peripheral Bus (3)
E8000050 to E80000FF
E8000110 to E80001FF
E8000206 to E800FFFF
10.2.3 Bus Timeout Detection Function
The bus timeout detection function detects bus accesses whose cycles are extended to 768 cycles
or more.
(1) Conditions of Bus Timeout Error Generation
Bus timeout errors occur in the following cases. This function should be used when debugging
software.
• A bus access is not completed on peripheral bus (1)
• A bus access is not completed on peripheral bus (3)
• The WAIT signal remains asserted during an external bus access
(2) Operation When a Bus Timeout Error is Generated
The operation when a bus timeout error occurs is explained below.
1. The timeout counter starts counting from the next cycle after the start of a bus access.
2. If the bus access is not completed in 768 cycles, a bus timeout occurs and an access canceling
signal is asserted for 256 cycles.
Bus signals such as address, data, BC, read/write, and burst are held.
The timeout error is recorded in the bus monitor status register 1 (SYCBESTS1) or bus
monitor status register 2 (SYCBESTS2).
A bus error interrupt is generated and sent to the CPU.
3. The bus access is terminated.
4. The CPU processes the bus error.
Locked buses are all released.
Rev. 2.00 Sep. 07, 2007 Page 302 of 1312
REJ09B0320-0200