SH7261 Datasheet, PDF (456/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
1
CMFV5
0
R/(W)*¹ Compare Match/Input Capture Flag V5
Status flag that indicates the occurrence of TGRV_5 input
capture or compare match.
[Setting conditions]
• When TCNTV_5 = TGRV_5 and TGRV_5 is
functioning as output compare register
• When TCNTV_5 value is transferred to TGRV_5 by
input capture signal while TGRV_5 is functioning as
input capture register
• When TCNTV_5 value is transferred to TGRV_5
while TGRV_5 is functioning as a register for
measuring the pulse width of the external input
signal*².
[Clearing condition]
• When 0 is written to CMFV5 after reading CMFV5 = 1
0
CMFW5
0
R/(W)*¹ Compare Match/Input Capture Flag W5
Status flag that indicates the occurrence of TGRW_5
input capture or compare match.
[Setting conditions]
• When TCNTW_5 = TGRW_5 and TGRW_5 is
functioning as output compare register
• When TCNTW_5 value is transferred to TGRW_5 by
input capture signal while TGRW_5 is functioning as
input capture register
• When TCNTW_5 value is transferred to TGRW_5
while TGRW_5 is functioning as a register for
measuring the pulse width of the external input
signal*².
[Clearing condition]
• When 0 is written to CMFW5 after reading CMFW5 =
1
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Timing to transfer is set by the IOC bit in the timer I/O control register U_5/V_5/W_5
(TIORU_5/V_5/W_5).
Rev. 2.00 Sep. 07, 2007 Page 424 of 1312
REJ09B0320-0200