SH7261 Datasheet, PDF (278/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
CKIO
A27 to A0
CSn
Ts Tw1 Tw2
Twn Tend Tdw1 Tdwn Tpw1
Tpwn Tend Tdw1 Tdwn Tnm
Tn1
Bus access (first time)
Bus access (second
and subsequent times)
Write cycle wait
Write data output
delay cycle
Page write
cycle wait
CS delay cycle
during write
(end only)
A0
CS assert wait
A1
CS delay cycle
during write
RD
WR
D31 to D0
WR assert wait
WR assert wait
Write data
output wait
Write data output Write data
delay cycle output wait
D0
Write data output
delay cycle
D1
Figure 9.5 Basic Bus Timing (Page Write Operation)
1. Ts (Internal Bus Access Start)
This is a bus access request cycle initiated by the internal bus master and with the external bus
as the target. CSn is always high during this cycle. In the next cycle A27 to A0 and the write
data change.
2. Tw1 to Twn (Read Cycle Wait, Write Cycle Wait)
For the first page access, the wait operation from internal bus access start to the wait end cycle
is the same as in normal access.
3. Tend (First Wait End Cycle)
This is the final cycle in the first series of read cycle wait or write cycle wait cycles. In write
access, the second and subsequent page accesses start from the next cycle, unless a write data
output delay cycle has been specified (with a value other than 0). The RD or WR signal is
negated (high level) in the next cycle if the RD assert wait or WD assert wait setting is other
than 0. If the RD assert wait or WD assert wait setting is 0, the RD or WR signal continues to
be asserted (low level). The CSn signal is not negated and continues to be asserted (low level).
In page read access, the succeeding bus access starts without waiting for the read data sample
cycle (Trd).
Rev. 2.00 Sep. 07, 2007 Page 246 of 1312
REJ09B0320-0200