SH7261 Datasheet, PDF (1022/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.51 Buffer Control Register (RINGBUFCTL)
RINGBUFCTL introduces a delay in the DMA transfer request signal in order to reduce the time
period over which the CD-ROM decoder is unable to respond due to ECC correction.
Data from the CD-ROM decoder may be transferred by DMA or by the CPU; the former is
triggered by asserting the DMA transfer request signal, while the latter is driven by the IREADY
interrupt. When either the DMAC or CPU is trying to get output data for which the input data
contained errors and is thus being subjected to ECC correction, a wait will be necessary because
the CD-ROM decoder cannot respond during ECC correction.
Bit: 7
6
5
4
—
DMREQDELAY
[1:0]
—
Initial value: 0
0
0
0
R/W: R/W R/W R/W R/W
3
—
0
R/W
2
—
0
R/W
1
—
0
R/W
0
—
0
R/W
Bit Bit Name
7

Initial
Value
0
6, 5 DMREQDELAY 00
[1:0]
4 to 0 
All 0
R/W Description
R/W Reserved
This bit is always read as 0.The write value should
always be 0.
R/W 00: Assertion of the DMA transfer request signal is not
delayed.
01: Assertion of the DMA transfer request signal is
delayed by 256 cycles.
10: Assertion of the DMA transfer request signal is
delayed by 512 cycles.
11: Assertion of the DMA transfer request signal is
delayed by 1024 cycles.
R/W Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 990 of 1312
REJ09B0320-0200