SH7261 Datasheet, PDF (1164/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
1
MSTP31 1
R/W Module Stop 31
When the MSTP31 bit is set to 1, the supply of the
clock to the DAC is halted.
0: DAC runs.
1: Clock supply to DAC halted.
0

1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
27.2.4 Standby Control Register 4 (STBCR4)
STBCR4 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR4 is initialized to H'FF by a power-on reset or in deep standby mode but
retains its previous value by a manual reset or in software standby mode. Only byte access is valid.
Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
47 46 45 44 43 42 41 40
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
MSTP47 1
R/W Module Stop 47
When the MSTP47 bit is set to 1, the supply of the
clock to the SCIF0 is halted.
0: SCIF0 runs.
1: Clock supply to SCIF0 halted.
6
MSTP46 1
R/W Module Stop 46
When the MSTP46 bit is set to 1, the supply of the
clock to the SCIF1 is halted.
0: SCIF1 runs.
1: Clock supply to SCIF1 halted.
Rev. 2.00 Sep. 07, 2007 Page 1132 of 1312
REJ09B0320-0200