SH7261 Datasheet, PDF (325/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
10.1.2 Bus Monitor Status Register 1 (SYCBESTS1)
SYCBESTS1 indicates the status of slave buses (peripheral bus (1)/peripheral bus (3)) regarding
whether a timeout occurred, whether an illegal address access was made, or which bus master
accessed the slave bus. Table 10.2 shows the correspondence between the bus spaces and the slave
buses.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— PTO PER — — — PMST[1:0] — CTO CER — — — CMST[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 15 
Initial
Value
All 0
14
PTO
0
13
PER
0
12 to 10 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Timeout
This bit indicates that a timeout occurred on peripheral
bus (1) when the first bus error occurred.
0: Timeout not generated
1: Timeout generated
R
Illegal Address Access
This bit indicates that an illegal address access was
made on peripheral bus (1) when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 293 of 1312
REJ09B0320-0200