SH7261 Datasheet, PDF (299/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(12) SDRAMC Setting Examples
The SDRAMC setting procedure, timing register setting examples, and the procedure for
transitioning to and recovering from self-refresh mode, power-down mode, and deep-power-down
mode are described below.
(a) SDRAMC Setting Procedure
Figure 9.26 shows the SDRAMC setting procedure.
Note that the specifications of the power-up sequence, etc., may vary depending on the SDRAM
used. Study the SDRAM specifications carefully before making system settings.
Rev. 2.00 Sep. 07, 2007 Page 267 of 1312
REJ09B0320-0200