SH7261 Datasheet, PDF (69/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Addressing Mode Instruction Format Effective Address Calculation
Equation
PC relative
disp:12
The effective address is the sum of PC value and
the value that is obtained by doubling the sign-
extended 12-bit displacement (disp).
PC + disp × 2
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
Rn
The effective address is the sum of PC value and PC + Rn
Rn.
PC
+
PC + Rn
Immediate
#imm:20
Rn
The 20-bit immediate data (imm) for the MOVI20 —
instruction is sign-extended.
31
19
0
Sign-
extended
imm (20 bits)
The 20-bit immediate data (imm) for the MOVI20S —
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits
are padded with zero.
31 27
8
0
imm (20 bits) 00000000
#imm:8
#imm:8
#imm:8
#imm:3
Sign-extended
The 8-bit immediate data (imm) for the TST, AND, —
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD, —
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA —
instruction is zero-extended and then quadrupled.
The 3-bit immediate data (imm) for the BAND,
—
BOR, BXOR, BST, BLD, BSET, and BCLR
instructions indicates the target bit location.
Rev. 2.00 Sep. 07, 2007 Page 37 of 1312
REJ09B0320-0200