SH7261 Datasheet, PDF (82/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
MOVA @(disp,PC),R0 11000111dddddddd disp × 4 + PC → R0
1
 Yes Yes Yes
MOVI20 #imm20,Rn
0000nnnniiii0000 imm → sign extension → Rn 1

Yes
iiiiiiiiiiiiiiii
MOVI20S #imm20,Rn
0000nnnniiii0001 imm << 8 → sign extension 1

Yes
iiiiiiiiiiiiiiii ^{→ Rn}
MOVML.L Rm,@-R15
0100mmmm11110001 R15-4 → R15, Rm → (R15) 1 to 16 
Yes
R15-4 → R15, Rm-1 → (R15)
:
R15-4 → R15, R0 → (R15)
Note: When Rm = R15, read
Rm as PR
MOVML.L @R15+,Rn
0100nnnn11110101 (R15) → R0, R15 + 4 → R15 1 to 16 
Yes
(R15) → R1, R15 + 4 → R15
:
(R15) → Rn
Note: When Rn = R15, read
Rm as PR
MOVMU.L Rm,@-R15
0100mmmm11110000 R15-4 → R15, PR → (R15) 1 to 16 
Yes
R15-4 → R15, R14 → (R15)
:
R15-4 → R15, Rm → (R15)
Note: When Rm = R15, read
Rm as PR
MOVMU.L @R15+,Rn
0100nnnn11110100 (R15) → Rn, R15 + 4 → R15 1 to 16 
Yes
(R15) → Rn + 1, R15 + 4 →
R15
:
(R15) → R14, R15 + 4 → R15
(R15) → PR
Note: When Rn = R15, read
Rm as PR
MOVRT Rn
0000nnnn00111001 ~T → Rn
1

Yes
MOVT Rn
0000nnnn00101001 T → Rn
1
 Yes Yes Yes
MOVU.B @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) →
1

Yes
1000dddddddddddd ^{zero extension → Rn}
MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp × 2 + Rm) →
1

Yes
1001dddddddddddd ^{zero extension → Rn}
Rev. 2.00 Sep. 07, 2007 Page 50 of 1312
REJ09B0320-0200