SH7261 Datasheet, PDF (889/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Power On/SW Reset*¹
Configuration Mode
MCR[0] = 1
(automatically in hardware reset only)
IRR[0] = 1, GSR[3] = 1 (automatically)
clear IRR[0] Bit
Configure MCR[15]
Clear Required IMR Bits
Mailbox Setting
(STD-ID, EXT-ID, LAFM, DLC,
RTR, IDE, MBC, MBIMR, DART,
ATX, NMC, Message-Data)*²
Set Bit Timing (BCR)
Clear MCR[0]
GSR[3] = 0?
Yes
No*³
RCAN-ET is in Tx_Rx Mode
Set TXPR to start transmission
or stay idle to receive
Transmission_Reception
(Tx_Rx) Mode
Detect 11 recessive bits and
Join the CAN bus activity
Receive*⁴
Transmit*⁴
Notes: 1. SW reset could be performed at any time by setting MCR[0] = 1.
2. Mailboxes are comprised of RAMs, therefore, please initialize all the mailboxes enabled by MBC.
3. It takes approximately 25 peripheral bus cycles for GSR[3] to be cleared to 0.
4. If there is no TXPR set, RCAN-ET will receive the next incoming message.
If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.
If it loses the arbitration, it will become a receiver.
Figure 19.6 Reset Sequence
Rev. 2.00 Sep. 07, 2007 Page 857 of 1312
REJ09B0320-0200