SH7261 Datasheet, PDF (256/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Bit
Bit Name
22 to 20 WRON
[2:0]
Initial
Value
000
19

0
18 to 16 RDON
000
[2:0]
15 to 11 
All 0
10 to 8 WDOFF 000
[2:0]
7

0
R/W Description
R/W WR Assert Wait Select
These bits specify the number of wait states inserted
before the external data write signal (WR3 to WR0) is
asserted.
000: 0 wait state
:
111: 7 wait states
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W RD Assert Wait Select
These bits specify the number of wait states inserted
before the external data read signal (RD) is asserted.
000: 0 wait state
:
111: 7 wait states
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Write Data Output Delay Cycle Select
These bits specify the number of cycles from the end of
the wait cycle during write operation (negation of the
WR3 to WR0 signals) and the negation of the external
data bus.
000: 0 wait state
:
111: 7 wait states
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 224 of 1312
REJ09B0320-0200