SH7261 Datasheet, PDF (370/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.10 DMA Activation Control Register (DMSCNT)
DMSCNT controls the operation of the DMAC.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — — — — — — DMST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 17 
Initial
Value
All 0
16
DMST
0
15 to 0 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W DMAC Module Activation
This bit is used to stop or activate the DMAC module.
When this bit is cleared to "0", the DMAC module
stops.
When this bit is set to "1", the DMAC module is
operational.
For details, see section 11.4.3, DMA Activation, and
section 11.6, Suspending, Restarting, and Stopping of
DMA Transfer.
0: DMAC halted
1: DMAC operating
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 338 of 1312
REJ09B0320-0200