SH7261 Datasheet, PDF (993/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Initial
Bit Bit Name Value
1
ST_SECS 0
0
ST_SECL 0
Section 21 CD-ROM Decoder (ROM-DEC)
R/W Description
R
Indicates that a sector has been processed as a short
sector with the aid of interpolated sync codes. If this bit
is set to 1, stop decoding immediately and retry the
procedure starting from the sector prior to the currently
being decoded sector.
R
Indicates that a sector has been processed as a long
sector with the aid of interpolated sync codes. If this bit
is set to 1, stop decoding immediately and retry the
procedure starting from two sectors prior to the sector
currently being decoded.
21.3.9 Post-ECC Header Error Status Register (CROMST1)
CROMST1 indicates error status in the post-ECC header.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
ER2_ ER2_ ER2_ ER2_
HEAD0 HEAD1 HEAD2 HEAD3
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R R
Bit Bit Name
7 to 4 
Initial
Value
All 0
3
ER2_HEAD0 0
2
ER2_HEAD1 0
1
ER2_HEAD2 0
0
ER2_HEAD3 0
R/W Description
R
Reserved
These bits are always read as 0 and cannot be
modified.
R
Indicates an error status in the minutes field of the
header after ECC correction.
R
Indicates an error status in the seconds field of the
header after ECC correction.
R
Indicates an error status in the frames (1/75 second)
field of the header after ECC correction.
R
Indicates an error status in the mode field of the header
after ECC correction.
Rev. 2.00 Sep. 07, 2007 Page 961 of 1312
REJ09B0320-0200