SH7261 Datasheet, PDF (1174/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Power-Down Modes
27.3 Operation
27.3.1 Sleep Mode
(1) Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules
continue to run in sleep mode. Clock pulses continue to be output on the CKIO pin.
(2) Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, H-UDI, IRQ, PINT, and on-chip peripheral
module), a bus error, or a reset (manual reset or power-on reset).
• Canceling with an interrupt
When an NMI, H-UDI, IRQ, PINT, or on-chip peripheral module interrupt occurs, sleep mode
is canceled and interrupt exception handling is executed. When the priority level of the
generated interrupt is equal to or lower than the interrupt mask level that is set in the status
register (SR) of the CPU, or the interrupt by the on-chip peripheral module is disabled on the
module side, the interrupt request is not accepted and sleep mode is not canceled.
• Canceling with a bus error
When a bus error occurs, sleep mode is canceled and bus error exception handling is executed.
• Canceling with a reset
Sleep mode is canceled by a power-on reset or a manual reset.
Rev. 2.00 Sep. 07, 2007 Page 1142 of 1312
REJ09B0320-0200