SH7261 Datasheet, PDF (260/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value
R/W Description
15 to 12 DREFW Undefined R/W Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count
[3:0]
Setting
These bits specify the number of auto-refresh cycles
and the number of self-refresh clearing cycles. The
DREFW bits can be written to at any time, regardless
of the state of the auto-refresh operation enable
(DRFEN) bit. If auto-refresh is disabled, the value
written to these bits takes effect immediately. If auto-
refresh is enabled, the value written to these bits takes
effect immediately if an auto-refresh cycle is not in
progress. If an auto-refresh cycle is in progress, the
new value takes effect after the cycle completes.
0000: 1 cycle
0001: 2 cycles
0010: 3 cycles
:
1111: 16 cycles
11 to 0 DRFC
[11:0]
Undefined R/W
Auto-Refresh Request Interval Setting
These bits specify the auto-refresh interval. The DRFC
bits can be written to at any time, regardless of the
state of the auto-refresh operation enable (DRFEN) bit.
If auto-refresh is disabled, the value written to these
bits takes effect immediately. If auto-refresh is enabled,
the value written to these bits is reflected in the
operation of the refresh counter from the next auto-
refresh request generated.
000000000000: Setting prohibited
000000000001: 2 cycles
000000000010: 3 cycles
:
111111111111: 4096 cycles
Note:
Auto-refresh requests are not accepted while multiple read or write accesses are in
progress, or during a transfer using DMAC, so the auto-refresh interval may become
enlarged in some cases. Set the DRFC bits to an auto-refresh request interval value that
satisfies the auto-refresh interval specification of the SDRAM being used. Furthermore,
make sure to set the auto-refresh request interval to a duration longer than the auto-refresh
cycle.
Rev. 2.00 Sep. 07, 2007 Page 228 of 1312
REJ09B0320-0200