SH7261 Datasheet, PDF (627/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(25) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Reset-Synchronized PWM Mode
Figure 12.149 shows an explanatory diagram of the case where an error occurs in complementary
PWM mode and operation is restarted in reset-synchronized PWM mode.
1
2
3
4
5
67
8
9 10 11 12 13 14 15 16 17
Power-on TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR
MTU2
reset
(CPWM) (1) (MTU2) (1)
occurs (PORT) (0) (normal) (0)
(RPWM) (1) (MTU2) (1)
module output
TIOC3A
TIOC3B
TIOC3D
Port output
PB16
PB17
PB19
High-Z
High-Z
High-Z
Figure 12.149 Error Occurrence in Complementary PWM Mode,
Recovery in Reset-Synchronized PWM Mode
1 to 10 are the same as in figure 12.145.
11. Set normal mode. (MTU2 output goes low.)
12. Disable channel 3 and 4 output with TOER.
13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling
with TOCR.
14. Set reset-synchronized PWM.
15. Enable channel 3 and 4 output with TOER.
16. Set MTU2 output with the PFC.
17. Operation is restarted by TSTR.
Rev. 2.00 Sep. 07, 2007 Page 595 of 1312
REJ09B0320-0200