SH7261 Datasheet, PDF (189/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Interrupt acceptance
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc + m1 + m2
3 Icyc
m1 m2 m3
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
F D E E M M M ^... M
F ^{... ...} D
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted
(Register Banking with Register Bank Overflow)
2 Icyc + 3 Bcyc + 1 Pcyc
2 Icyc + 17(m4)
1 Icyc + m1 + m2 + 2(m4)
IRQ
m4 m4
m1 m2 m3
RESBANK instruction
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
F D E M M M ... M M M W
D E E M M M ^...
F ^... D
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
m4: Restoration of banked registers
Interrupt acceptance
Figure 6.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
Instruction Execution (Register Banking with Register Bank Overflow)
Rev. 2.00 Sep. 07, 2007 Page 157 of 1312
REJ09B0320-0200