SH7261 Datasheet, PDF (197/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
Section 7 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Instruction fetch or data read/write of CPU, data
size, data contents, address value, and stop timing in the case of instruction fetch are break
conditions that can be set in the UBC. Since this LSI uses a Harvard architecture, instruction fetch
on the CPU bus (C bus) is performed by issuing bus cycles on the instruction fetch bus (F bus),
and data access on the C bus is performed by issuing bus cycles on the memory access bus (M
bus). The UBC monitors the C bus and internal bus (I bus).
7.1 Features
1. The following break comparison conditions can be set.
Number of break channels: two channels (channels 0 and 1)
User break can be requested as the independent condition on channels 0 and 1.
• Address
Comparison of the 32-bit address is maskable in 1-bit units.
One of the three address buses (F address bus (FAB), M address bus (MAB), and I address bus
(IAB)) can be selected.
• Data
Comparison of the 32-bit data is maskable in 1-bit units.
One of the two data buses (M data bus (MDB) and I data bus (IDB)) can be selected.
• Bus cycle
Instruction fetch (only when C bus is selected) or data access
• Read/write
• Operand size
Byte, word, and longword
2. In an instruction fetch cycle, it can be selected whether the start of user break interrupt
exception processing is set before or after an instruction is executed.
3. When a break condition is satisfied, a trigger signal is output from the UBCTRG pin.
Rev. 2.00 Sep. 07, 2007 Page 165 of 1312
REJ09B0320-0200