SH7261 Datasheet, PDF (118/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
Clock
Operating
Mode
FRQCR
Setting
PLL Frequency
Multiplier
PLL
PLL
Circuit 1 Circuit 2
Ratio of
Internal Clock
Frequencies
(I:B:P)*¹
Input Clock*²
Selectable Frequency Range (MHz)
Output Clock Internal Clock Bus Clock
(CKIO Pin)*³ (Iφ)*³
(Bφ)*³
Peripheral
Clock (Pφ)*³
3
H'1404 ON (×6) OFF
6:1:1
20

120
20
20
H'1406 ON (×6) OFF
6:1:1/2
20

120
20
10
H'1414 ON (×6) OFF
3:1:1
20 to 33.33 
60 to 100
20 to 33.33 20 to 33.33
H'1416 ON (×6) OFF
3:1:1/2
20 to 33.33 
60 to 100
20 to 33.33 10 to 16.67
H'1424 ON (×6) OFF
2:1:1
20 to 33.33 
40 to 66.67 20 to 33.33 20 to 33.33
H'1426 ON (×6) OFF
2:1:1/2
20 to 33.33 
40 to 66.67 20 to 33.33 10 to 16.67
H'1444 ON (×6) OFF
1:1:1
20 to 33.33 
20 to 33.33 20 to 33.33 20 to 33.33
H'1446 ON (×6) OFF
1:1:1/2
20 to 33.33 
20 to 33.33 20 to 33.33 10 to 16.67
H'1515 ON (×8) OFF
4:1:1
20 to 25

80 to 100
20 to 25
20 to 25
H'1535 ON (×8) OFF
2:1:1
20 to 25

40 to 50
20 to 25
20 to 25
H'1555 ON (×8) OFF
1:1:1
20 to 25

20 to 25
20 to 25
20 to 25
Notes:
Caution:
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
2. In modes 0 and 2, the frequency of the clock input from the EXTAL pin or the
frequency of the crystal resonator. In mode 3, the frequency of the clock input from
the CKIO pin.
3. Use an internal clock (Iφ) frequency of 120 MHz or lower for the regular specifications
and 100 MHz or lower for the wide-range specifications. Use a CKIO pin or bus clock
(Bφ) frequency of 60 MHz or lower. Pφ must be from 5 through 40 MHz.
1. The frequency of the internal clock is the frequency of the signal input to the CKIO
pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the
divider's divisor. Do not set a frequency for the internal clock below the frequency of
the signal on the CKIO pin.
2. The frequency of the peripheral clock is the frequency of the signal input to the CKIO
pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the
divider's divisor. Set the frequency of the peripheral clock to 40 MHz or below. In
addition, do not set a higher frequency for the internal clock than the frequency on
the CKIO pin.
3. The frequency multiplier of PLL circuit 1 can be selected as ×1, ×2, ×3, ×4, ×6, or ×8.
The divisor of the divider can be selected as ×1, ×1/2, ×1/3, ×1/4, ×1/6, ×1/8, or
×1/12. The settings are made in the frequency-control register (FRQCR).
4. The signal output by PLL circuit 1 is the signal on the CKIO pin multiplied by the
frequency multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL
circuit 1 is not more than 200 MHz.
Rev. 2.00 Sep. 07, 2007 Page 86 of 1312
REJ09B0320-0200