SH7261 Datasheet, PDF (347/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
2. Set this register so that DMA transfer is performed within the correctly aligned address
boundaries for the transfer sizes listed below.
• When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
• When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
3. Only write to this register when single operand transfer is not in process on the
corresponding channel (the corresponding DASTS bit in the DMA arbitration status
register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation
control register (DMSCNT) or DEN in DMA control register B for the channel
(DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when
both conditions are not satisfied.
11.3.4 DMA Reload Source Address Register (DMRSADR)
DMRSADR is used to set an address for reloading to the DMA current source address register
(DMCSADRn).
To enable reloading, set the DMA source address reload function enable bit (SRLOD) in DMA
control register A (DMCNTAn) for the channel to "1". In this case, set both the DMA current
source address register (DMCSADRn) and DMA reload source address register (DMRSADRn).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSA
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RSA
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 0 RSA
Undefined R/W Holds source address bits A31 to A0 for reloading
Note: Set this register so that DMA transfer is performed within the correctly aligned address
boundaries for the transfer sizes listed below.
• When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
• When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
Rev. 2.00 Sep. 07, 2007 Page 315 of 1312
REJ09B0320-0200