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| SH7261 Datasheet, PDF (969/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Section 20 IEBusTM Controller (IEB) [R5S72612] [R5S72613]
20.6.3 Master Receive Operation
Figure 20.15 shows the timing for master receive operation.
Slave
reception
DL
Dn-1 Dn
Master
reception
HD MA SA CT DL D1 D2
IECMR
IEFLG
CMX
MRQ
SRQ
Master transmission request
SRE
IETSR
RXS
RXF
[Legend]
HD: Header
MA: Master address field
SA: Slave address field
CT: Control field
DL: Message length field
Dn: Data field
Figure 20.15 Master Receive Operation Timing
Dn-1 Dn
Rev. 2.00 Sep. 07, 2007 Page 937 of 1312
REJ09B0320-0200
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