SH7261 Datasheet, PDF (778/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
17.3.7 I²C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
empty space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT
to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. ICDRT is initialized to H'FF.
ICDRT is initialized to H'FF by a power-on reset or deep standby mode.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
17.3.8 I²C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register.
ICDRR is initialized to H'FF by a power-on reset or deep standby mode.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R R R R R R R R
17.3.9 I²C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value: — — — — — — — —
R/W: — — — — — — — —
Rev. 2.00 Sep. 07, 2007 Page 746 of 1312
REJ09B0320-0200