SH7261 Datasheet, PDF (362/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Table 11.4 Relationships between DMA Request Sources and Input Sense Mode
DMA Request
Source
Software trigger
DREQ0 pin
DREQ1 pin
DREQ2 pin
DREQ3 pin
IIC3 0ch RX
IIC3 0ch TX
IIC3 1ch RX
IIC3 1ch TX
IIC3 2ch RX
IIC3 2ch TX
SCIF 0ch RX
SCIF 0ch TX
SCIF 1ch RX
SCIF 1ch TX
SCIF 2ch RX
SCIF 2ch TX
SCIF 3ch RX
SCIF 3ch TX
SCIF 4ch RX
SCIF 4ch TX
SCIF 5ch RX
SCIF 5ch TX
SCIF 6ch RX
SCIF 6ch TX
SCIF 7ch RX
SCIF 7ch TX
00: Rising
Edge Sense
√
√
√
√
√
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
STRG Bit Settings
01: High
10: Falling
Level Sense Edge Sense
×
×
√
√
√
√
√
√
√
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
×
√
11: Low Level DCTG Bit
Sense
Setting
×
000000
√
000001
√
000010
√
000011
√
000100
×
000101
×
000110
×
000111
×
001000
×
001001
×
001010
×
001011
×
001100
×
001101
×
001110
×
001111
×
010000
×
010001
×
010010
×
010011
×
010100
×
010101
×
010110
×
010111
×
011000
×
011001
×
011010
Rev. 2.00 Sep. 07, 2007 Page 330 of 1312
REJ09B0320-0200