SH7261 Datasheet, PDF (720/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
4
BRK
0
R/(W)* Break Detection
Indicates that a break signal has been detected in
receive data.
0: No break signal received
[Clearing conditions]
• BRK is cleared to 0 when the chip is a power-on
reset
• BRK is cleared to 0 when software reads BRK
after it has been set to 1, then writes 0 to BRK
1: Break signal received*¹
[Setting condition]
• BRK is set to 1 when data including a framing
error is received, and a framing error occurs with
space 0 in the subsequent receive data
Note: 1. When a break is detected, transfer of the
receive data (H'00) to SCFRDR stops after
detection. When the break ends and the
receive signal becomes mark 1, the transfer
of receive data resumes.
3
FER
0
R
Framing Error Indication
Indicates a framing error in the data read from the
next receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No receive framing error occurred in the next data
read from SCFRDR
[Clearing conditions]
• FER is cleared to 0 when the chip undergoes a
power-on reset
• FER is cleared to 0 when no framing error is
present in the next data read from SCFRDR
1: A receive framing error occurred in the next data
read from SCFRDR.
[Setting condition]
• FER is set to 1 when a framing error is present in
the next data read from SCFRDR
Rev. 2.00 Sep. 07, 2007 Page 688 of 1312
REJ09B0320-0200