SH7261 Datasheet, PDF (724/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the
CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive
bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset
or in deep standby mode. Each channel has independent baud rate generator control, so different
values can be set in eight channels.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The SCBRR setting is calculated as follows:
• Asynchronous mode:
N=
Pφ
× 10⁶ − 1
64 × 2^2n-1 × B
• Clocked synchronous mode:
N=
Pφ
× 10⁶ − 1
8 × 2^2n-1 × B
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting must satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
see table 16.3.)
Rev. 2.00 Sep. 07, 2007 Page 692 of 1312
REJ09B0320-0200