SH7261 Datasheet, PDF (639/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
13.3.5 Timer Counter Control Register (TCCR)
TCCR selects the TCNT internal clock source and controls external reset input.
Bit: 7
6
5
4
3
2
1
0
— — — — TMRIS — ICKS[1:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 4
Bit Name

Initial
Value
All 0
3
TMRIS 0
2

0
1, 0 ICKS[1:0] 00
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Timer Reset Input Select
Selects an external reset input when the CCLR1 and
CCLR0 bits in TCR are B'11.
0: Cleared at rising edge of the external reset
1: Cleared when the external reset is high
Reserved
This bit is always read as 0. The write value should
always be 0
Internal Clock Select 1 and 0
These bits in combination with bits CKS2 to CKS0 in TCR
select the internal clock. See table 13.2.
Rev. 2.00 Sep. 07, 2007 Page 607 of 1312
REJ09B0320-0200