SH7261 Datasheet, PDF (703/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.2 Input/Output Pins
Table 16.1 shows the pin configuration of the SCIF.
Table 16.1 Pin Configuration
Channel
0 to 7
Pin Name
Serial clock pins
Receive data pins
Transmit data pins
Symbol
SCK0 to SCK7
RxD0 to RxD7
TxD0 to TxD7
I/O
I/O
Input
Output
Function
Clock I/O
Receive data input
Transmit data output
16.3 Register Descriptions
The SCIF has the following registers.
Table 16.2 Register Configuration
Channel
0
Register Name
Abbreviation R/W
Initial Value Address
Serial mode register_0
SCSMR_0
R/W
H'0000
H'FFFE8000
Bit rate register_0
SCBRR_0
R/W
H'FF
H'FFFE8004
Serial control register_0
SCSCR_0
R/W
H'0000
H'FFFE8008
Transmit FIFO data register_0 SCFTDR_0
Serial status register_0
SCFSR_0
W
Undefined
R/(W)*¹ H'0060
H'FFFE800C
H'FFFE8010
Receive FIFO data register_0 SCFRDR_0 R
Undefined H'FFFE8014
FIFO control register_0
SCFCR_0
R/W
H'0000
H'FFFE8018
FIFO data count register_0
SCFDR_0
R
H'0000
H'FFFE801C
Serial port register_0
Line status register_0
SCSPTR_0
SCLSR_0
R/W
H'0050
R/(W)*² H'0000
H'FFFE8020
H'FFFE8024
Access
Size
16
8
16
8
16
8
16
16
16
16
Rev. 2.00 Sep. 07, 2007 Page 671 of 1312
REJ09B0320-0200