SH7261 Datasheet, PDF (15/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC) ...................................305
11.1 Features.............................................................................................................................. 305
11.2 Input/Output Pins ............................................................................................................... 307
11.3 Register Descriptions ......................................................................................................... 308
11.3.1 DMA Current Source Address Register (DMCSADR) ........................................ 312
11.3.2 DMA Current Destination Address Register (DMCDADR) ................................ 313
11.3.3 DMA Current Byte Count Register (DMCBCT) .................................................. 314
11.3.4 DMA Reload Source Address Register (DMRSADR) ......................................... 315
11.3.5 DMA Reload Destination Address Register (DMRDADR) ................................. 316
11.3.6 DMA Reload Byte Count Register (DMRBCT) ................................................... 317
11.3.7 DMA Mode Register (DMMOD) ......................................................................... 318
11.3.8 DMA Control Register A (DMCNTA) ................................................................. 324
11.3.9 DMA Control Register B (DMCNTB) ................................................................. 332
11.3.10 DMA Activation Control Register (DMSCNT).................................................... 338
11.3.11 DMA Interrupt Control Register (DMICNT) ....................................................... 339
11.3.12 DMA Common Interrupt Control Register (DMICNTA)..................................... 340
11.3.13 DMA Interrupt Status Register (DMISTS) ........................................................... 341
11.3.14 DMA Transfer End Detection Register (DMEDET) ............................................ 342
11.3.15 DMA Arbitration Status Register (DMASTS)...................................................... 344
11.4 Operation ........................................................................................................................... 346
11.4.1 DMA Transfer Mode ............................................................................................ 346
11.4.2 DMA Transfer Condition...................................................................................... 348
11.4.3 DMA Activation ................................................................................................... 352
11.5 Completion of DMA Transfer and Interrupts .................................................................... 353
11.5.1 Completion of DMA Transfer .............................................................................. 353
11.5.2 DMA Interrupt Requests....................................................................................... 354
11.5.3 DMA End Signal Output ...................................................................................... 356
11.6 Suspending, Restarting, and Stopping of DMA Transfer .................................................. 358
11.6.1 Suspending and Restarting DMA Transfer ........................................................... 358
11.6.2 Stopping DMA Transfer on Any Channel ............................................................ 358
11.7 DMA Requests................................................................................................................... 359
11.7.1 Sources of DMA Requests.................................................................................... 359
11.7.2 Synchronous Circuits for DMA Request Signals.................................................. 359
11.7.3 Sense Mode for DMA Requests............................................................................ 360
11.8 Determining DMA Channel Priority.................................................................................. 363
11.8.1 Channel Priority Order.......................................................................................... 363
11.8.2 Operation during Multiple DMA Requests........................................................... 363
11.8.3 Output of the DMA Acknowledge and DNA Active Signals ............................... 364
11.9 Units of Transfer and Positioning of Bytes for Transfer.................................................... 366
Rev. 2.00 Sep. 07, 2007 Page xv of xxxii