SH7261 Datasheet, PDF (844/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Important: Although core of RCAN-ET is designed based on a 32-bit bus system, the whole
RCAN-ET including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord
(32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual,
LongWord access means the two consecutive accesses.
19.2.2 Functions of Each Block
(1) Micro Processor Interface (MPI)
The MPI allows communication between the Renesas CPU and RCAN-ET's registers/mailboxes to
control the memory interface. It also contains the Wakeup Control logic that detects the CAN bus
activities and notifies the MPI and the other parts of RCAN-ET so that the RCAN-ET can
automatically exit the Sleep mode.
It contains registers such as MCR, IRR, GSR and IMR.
(2) Mailbox
The Mailboxes consists of RAM configured as message buffers and registers. There are 16
Mailboxes, and each mailbox has the following information.
<RAM>
• CAN message control (identifier, rtr, ide,etc)
• CAN message data (for CAN Data frames)
• Local Acceptance Filter Mask for reception
<Registers>
• CAN message control (dlc)
• 3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, Auto-
Transmission for Remote Request bit, New Message Control bit
Rev. 2.00 Sep. 07, 2007 Page 812 of 1312
REJ09B0320-0200