SH7261 Datasheet, PDF (152/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
NMI
IRQ7 to IRQ0
PINT7 to PINT0
UBC
H-UDI
ADC
ROM-DEC
MTU2
RTC
WDT
IIC3
DMAC
SCIF
RCAN-ET
IEB
SSI
TMR
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Input control
Priority
identifier
ICR0
ICR2
PINTER
IBCR
ICR1
IRQRR
PIRR
IBNR
IPR
IPR01, IPR02,
IPR05 to IPR16
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
Module bus
Bus
interface
[Legend]
UBC:
User break controller
H-UDI: User debugging interface
ADC:
A/D converter
ROM-DEC: CD-ROM decoder
MTU2: Multi-function timer pulse unit 2
RTC:
Realtime clock
WDT:
Watchdog timer
IIC3:
I²C bus interface 3
DMAC: Direct memory access controller
SCIF:
Serial communication interface with FIFO
RCAN-ET: Controller area network
IEB:
IEBus^TM controller
SSI:
Serial sound interface
INTC
TMR: 8-bit timer
ICR0: Interrupt control register 0
ICR1: Interrupt control register 1
ICR2: Interrupt control register 2
IRQRR: IRQ interrupt request register
PINTER: PINT interrupt enable register
PIRR: PINT interrupt request register
IBCR: Bank control register
IBNR: Bank number register
IPR01, IPR02, IPR05 to IPR16:
Interrupt priority registers 01, 02, 05 to 16
Figure 6.1 Block Diagram of INTC
Rev. 2.00 Sep. 07, 2007 Page 120 of 1312
REJ09B0320-0200