SH7261 Datasheet, PDF (1042/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Table 21.4 Number of Wait Cycles for Reading STRMDOUT0 and STRMDOUT1
Registers
Number of ECC
Corrections
1
Number of Wait
Cycles
370 to 1400
2
720 to 1900
3
1070 to 2400
Number of Wait Cycles when Delay is Introduced
DMAREQDELAY[1:0]
Setting
Number of Wait Cycles
0
370 to 1040
1
114 to 1144
2
0 to 888
3
0 to 376
0
720 to 1900
1
464 to 1644
2
208 to 1388
3
0 to 876
0
1070 to 2400
1
814 to 2144
2
558 to 1888
3
46 to 1376
When the number of the ECC correction is 1 and the DMAREQDELAY[1:0] setting is 3, the
period of waiting is up to 376 cycles. If the CD-ROM decoding is not completed in this waiting
time, take the waiting time into account in software for DMAC activation.
In addition, the effect of DMAREQDELAY[1:0] in reducing the wait only applies to the DMA
activation signal. Since the IREADY interrupt cannot be delayed, waiting time must be taken into
account in the software if the STRMDOUT0 and STRMDOUT1 registers are to be read by the
CPU.
21.6.5 Stopping and Resuming CD-DSP Operation
When stopping and resuming the stream data input to the CD-ROM decoder, note that the input
data stream does not stop immediately before a sync code and that the CD-ROM decoder may
recognize the data as incorrect when the input stream is resumed. This happens because the system
holds a combination of the data up to the point where input was stopped and data that is input from
the point of resumption. Take care on this point when stopping and resuming input.
Rev. 2.00 Sep. 07, 2007 Page 1010 of 1312
REJ09B0320-0200