SH7261 Datasheet, PDF (200/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
7.3.1 Break Address Register (BAR)
BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in
each channel. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the
three address buses for a break condition. BAR is initialized to H'00000000 by a power-on reset or
in deep standby, but retains its previous value by a manual reset or in software standby mode or
sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BA31 to BA0 All 0
R/W Break Address
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions.
When the C bus and instruction fetch cycle are
selected by BBR, specify an FAB address in bits BA31
to BA0.
When the C bus and data access cycle are selected by
BBR, specify an MAB address in bits BA31 to BA0.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0.
Rev. 2.00 Sep. 07, 2007 Page 168 of 1312
REJ09B0320-0200