SH7261 Datasheet, PDF (290/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(7) Power-Down Mode
SDRAMC supports an SDRAM power-down mode. In power-down mode the SDCKE signal from
SDRAMC goes low level. While in power-down mode auto-refresh operations are performed at
the interval specified by the auto-refresh request interval setting (DRFC) bits in SDRAM refresh
control register 1 (SDRFCNT1). The SDCKE signal only goes high when an auto-refresh
command is issued.
Transition to and recovery from power-down mode are performed using the SDRAM power-down
control register (SDPWDCNT).
Setting the DPWD bit to 1 causes SDRAMC to transition to power-down mode. Clearing the
DPWD bit to 0 causes SDRAMC to recover from power-down mode.
The SDCKE signal from SDRAMC goes high level when recovery from power-down mode
occurs.
CKIO
SDRAMC power-down mode
SDCKE
Figure 9.11 SDRAMC Power-Down Mode
SDRAMC power-down mode
CKIO
SDCKE
SDRAM command
RFA
Auto-refresh command
Figure 9.12 Auto-Refresh Operation in SDRAMC Power-Down Mode
Rev. 2.00 Sep. 07, 2007 Page 258 of 1312
REJ09B0320-0200