SH7261 Datasheet, PDF (349/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.6 DMA Reload Byte Count Register (DMRBCT)
DMRBCT is a register used to set the number for reloading to the DMA current byte count
register (DMCBCTn).
To enable reloading, set the DMA byte count reload function enable bit (BRLOD) in the DMA
control register A (DMCNTAn) to 1. In this case, set both the DMA current byte count register
(DMCBTn) and DMA reload byte count address register (DMRBCTn).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
——————
RBC
Initial value: 0
0
0
0
0
0 ——————————
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RBC
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 26 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 0 RBC
Undefined R/W Number of bytes to be DMA-transferred after reloading
Note: Set this register so that DMA transfer is performed within the correctly aligned address
boundaries for the transfer sizes listed below.
• When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
• When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
Rev. 2.00 Sep. 07, 2007 Page 317 of 1312
REJ09B0320-0200