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SH7261 Datasheet, PDF (801/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Section 17 I2C Bus Interface 3 (IIC3)
Table 17.5 Time for Monitoring SCL
CKS3
CKS2
Time for Monitoring SCL*1
0
0
9 tpcyc*2
1
21 tpcyc*2
1
0
33 tpcyc*2
1
81 tpcyc*2
Notes: 1. Monitors the (on-board) SCL level after the time (pcyc) for monitoring SCL has passed
since the rising edge of the SCL monitor timing reference clock.
2. pcyc = Pφ × cyc
Rev. 2.00 Sep. 07, 2007 Page 769 of 1312
REJ09B0320-0200