SH7261 Datasheet, PDF (585/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Phase
Phase
differ-
differ-
Overlap ence Overlap ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 12.108 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
12.7.3 Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
• Channels 0 to 4
Pφ
f=
(N + 1)
• Channel 5
f = ^Pφ
N
Where f:
Counter frequency
Pφ: MTU2 peripheral clock operating frequency
N: TGR set value
Rev. 2.00 Sep. 07, 2007 Page 553 of 1312
REJ09B0320-0200